Serial-to-parallel converters are used to convert serial input data into parallel data in active matrix displays, for example. FIG. 1 shows a typical serial-to-parallel converter using D-type Flip Flops (DFFs). A four-stage shift register 2 stores four samples of the serial input data DIN. The shift register outputs Q1-4 are then simultaneously sampled by output DFFs 4, which hold the data on outputs DOUT1-4 until the next four samples have been stored.
FIG. 2 shows an alternative serial-to-parallel converter composed of DFFs. Serial input data DIN is common to four DFFs 10-16 controlled by separate sampling signals SMP1-4. Four samples of DIN are stored and, again, outputs Q1-4 are simultaneously sampled by output DFFs 18, which hold the data on outputs DOUT1-4 until the next four samples have been stored.
In both FIG. 1 and FIG. 2, the output latches 4 and 18 respectively are activated by the rising edge of the transfer signal TRAN. This needs to occur when the correct data is present on Q1-4. Otherwise, incorrect data will be sampled and held on DOUT1-4. This may occur due to timing errors introduced by signal propagation delays within the display.
FIGS. 3 and 4 show a typical DFF and its operation respectively. When CK is low, the first and second D-Latches (DLs) are transparent and latched respectively. When CK is high, the first DL is latched and its output passed to Q via the now transparent second latch. The DFF itself is not transparent since the first DL is latched when CK is high. In this way, transitions in Q only occur on the rising edges of CK when Q is latched.
US patent publication 2009/0040082 (Hinz et al., published 12 Feb. 2009) details a serial-to-parallel converter using DFFs. However, DFFs consume more power than DLs, occupy a larger layout area and have lower yield.